XC164-16 Datasheet, PDF (135/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Capture/Compare Units
in the same clock cycle. This mode offers a faster operation and increased resolution of
the CAPCOM unit, 8 times higher than in staggered mode.
Staggered Mode
Figure 17-12 illustrates the staggered mode operation. In this example, all CCy registers
are programmed for compare mode 3.
Registers CC0, CC1, and CC2 are all programmed for a compare value of FFFE_H. When
the timer increments to FFFE_H, the comparator detects a match for all of the three
registers. The output CC0IO of register CC0 is switched to 1 one cycle after the
comparator match. However, the outputs CC1IO and CC2IO are not switched at the
same time, but one, respectively two cycles later. This staggering of the outputs
continues for all registers including register CC7. The number of the register indicates
the delay of the output signal in clock cycles - the output of register CC7 is switched
7 cycles later than the one of register CC0. In the example, the compare value for
register CC7 is set to FFFD_H. Thus, the output is switched in the last clock cycle of the
CAPCOM cycle in which the timer reached FFFD_H.
When the timer overflows, all compare outputs are reset to 0 (compare mode 3). Again,
the staggering of the output signals can be seen from Figure 17-12.
Looking at registers CC8 through CC15 shows that their outputs are switched in parallel
to the respective outputs of registers CC0 through CC15. In fact, the staggering is
performed in parallel for the upper and the lower register bank. In this way, it is assured,
that both compare signals of a register pair in double-register compare mode operate
simultaneously.
In staggered mode direct port latch switching (see Section 17.6) is possible. However,
it is possible to use the alternate output function option of the associated port pins to
output the compare signals.
Note: This is a general description and only refers to channels connected to pins.
User’s Manual
CC12_X41, V2.1
17-30
V2.1, 2004-03