XC164-16 Datasheet, PDF (247/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Asynchronous/Synchronous Serial Interface (ASC)
19.4
Baudrate Generation
The serial channel ASC has its own dedicated 13-bit baudrate generator with reload
capability, allowing baudrate generation independent of other timers.
The baudrate generator is clocked with a clock (f_DIV) derived via a prescaler from the
ASC input clock f_ASC. The baudrate timer counts downwards and can be started or
stopped through the baudrate generator run bit R. Each underflow of the timer provides
one clock pulse to the serial channel. The timer is reloaded with the value stored in its
13-bit reload register each time it underflow. The resulting clock f_BRT is again divided by
a factor for the baudrate clock (16 in Asynchronous Modes and 4 in Synchronous Mode).
The prescaler is selected by the bits BRS and FDE. In addition to the two fixed dividers,
a fractional divider prescaler unit is available in the Asynchronous Modes that allows
selection of prescaler divider ratios of n/512 with n = 0 … 511. Therefore, the baudrate
of ASC is determined by the module clock, the content of FDV, the reload value of BG,
and the operating mode (asynchronous or synchronous).
Register ASCx_BG is the dual-function Baudrate Generator/Reload register. Reading
ASCx_BG returns the contents of the timer BR_VALUE (bits 15 … 13 return zero), while
writing to BG always updates the reload register (bits 15 … 13 are insignificant).
An autoreload of the timer with the contents of the reload register is performed each time
ASCx_BG is written to. However, if bit R is cleared at the time a write operation to
ASCx_BG is performed, the timer will not be reloaded until the first instruction cycle after
bit R was set. For a clean baudrate initialization, ASCx_BG should be written only if
R = 0. If ASCx_BG is written while R = 1, unpredictable behavior of the ASC may occur
during running transmit or receive operations.
The ASC baudrate timer reload register ASCx_BG contains the 13-bit reload value for
the baudrate timer in Asynchronous and Synchronous modes.
19.4.1 Baudrate in Asynchronous Mode
For Asynchronous Mode, the baudrate generator provides a clock f_BRT with sixteen times
the rate of the established baudrate. Every received bit is sampled at the 7^th, 8^th, and 9^th
cycle of this clock. The clock divider circuitry, which generates the input clock for the
13-bit baudrate timer, is extended by a fractional divider circuitry that allows adjustment
for more accurate baudrate and the extension of the baudrate range.
The baudrate of the baudrate generator depends on the following bits and register
values:
• Input clock f_ASC
• Selection of the baudrate timer input clock f_DIV by bits FDE and BRS
• If bit FDE is set (fractional divider): value of register ASCx_FDV
• Value of the 13-bit reload register ASCx_BG
User’s Manual
ASC_X, V2.0
19-22
V2.1, 2004-03