XC164-16 Datasheet, PDF (130/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Capture/Compare Units
17.6
Compare Output Signal Generation
This section discusses the interaction between the CAPCOM Unit and the Port Logic.
The block diagram illustrated in Figure 17-11 details the logic of the block “Mode &
Output Control”, shown in Figure 17-5, Figure 17-7, and Figure 17-10.
Each output signal is latched in its associated bit of the respective output latch register
CCx_OUT. The individual bits are updated each time an associated compare event
occurs. The bits of these registers are connected to the respective port pins as an
alternate output function of a port line.
Compare signals can also directly affect the associated port output latch Px. In this case,
the port latch must be selected for the respective pin. The direct port latch option is
disabled in non-staggered mode or it can be disabled by setting bit PL in register
CCx_IOC.
Register CCx_OUT is always updated in parallel to the update of the port output latch.
CC1_OUT
Compare Output Reg.
SFR (FF5C_H/AE_H)
Reset Value: 0000_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC
15
IO
CC
14
IO
CC
13
IO
CC
12
IO
CC
11
IO
CC
10
IO
CC9 CC8 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0
IO IO IO IO IO IO IO IO IO IO
rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh
CC2_OUT
Compare Output Reg.
SFR (FF2C_H/96_H)
Reset Value: 0000_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC
15
IO
CC
14
IO
CC
13
IO
CC
12
IO
CC
11
IO
CC
10
IO
CC9 CC8 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0
IO IO IO IO IO IO IO IO IO IO
rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh
Field
CCyIO
Bits Type
15 … 0 rwh
Description
Compare Output for Channel y
Alternative port output for the associated port pin.
User’s Manual
CC12_X41, V2.1
17-25
V2.1, 2004-03