XC164-16 Datasheet, PDF (34/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
For counter operation, pin TxIN must be configured as input (the respective direction
control bit DPx.y must be 0). The maximum input frequency allowed in counter mode
depends on the selected prescaler value. To ensure that a transition of the count input
signal applied to TxIN is recognized correctly, its level must be held high or low for a
minimum number of module clock cycles before it changes. This information can be
found in Section 14.1.5.
Timers T2 and T4 in Incremental Interface Mode
Incremental interface mode for an auxiliary timer Tx is selected by setting bitfield TxM in
the respective register TxCON to 110_B or 111_B. In incremental interface mode, the two
inputs associated with an auxiliary timer Tx (TxIN, TxEUD) are used to interface to an
incremental encoder. Tx is clocked by each transition on one or both of the external input
pins to provide 2-fold or 4-fold resolution of the encoder input.
TxIN
Edge
Select
0
TxI TxR
MUX
1
T3R
Count _Auxiliary
Timer Tx
Overflow
Underflow
Tx
Edge
Tx
RDIR
TxEUD
TxUD
Phase
Detect
TxRC
0
=1
MUX
1
Change
Detect
TxM
TxUDE
TxCH
DIR
TxM
&
>^_ 1
TxIRQ
&
TxIRDIS
MCB05398
Figure 14-14 Block Diagram of an Auxiliary Timer in Incremental Interface Mode
The operation of the auxiliary timers T2 and T4 in incremental interface mode and the
interrupt generation are the same as described for the core timer T3. The descriptions,
figures and tables apply accordingly.
User’s Manual
GPT_X41, V2.0
14-21
V2.1, 2004-03