XC164-16 Datasheet, PDF (24/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
Incremental Interface Mode
Incremental interface mode for the core timer T3 is selected by setting bitfield T3M in
register T3CON to 110_B or 111_B. In incremental interface mode, the two inputs
associated with core timer T3 (T3IN, T3EUD) are used to interface to an incremental
encoder. T3 is clocked by each transition on one or both of the external input pins to
provide 2-fold or 4-fold resolution of the encoder input.
T3IN
T3EUD
Edge
Select
T3I
T3UD
Phase
Detect
Count
Core
Timer T3
T3R
T3
EDGE
T3
RDIR
0
=1
MUX
1
Change
Detect
T3M
T3UDE
T3CH
DIR
Toggle
Latch
>^_1
T3OUT
to
T2/T4
T3IRQ
T3M
MCB05394
Figure 14-7 Block Diagram of Core Timer T3 in Incremental Interface Mode
Bitfield T3I in control register T3CON selects the triggering transitions (see Table 14-3).
The sequence of the transitions of the two input signals is evaluated and generates count
pulses as well as the direction signal. So T3 is modified automatically according to the
speed and the direction of the incremental encoder and, therefore, its contents always
represent the encoder’s current position.
The interrupt request (T3IRQ) generation mode can be selected: In Rotation Detection
Mode (T3M = 110_B), an interrupt request is generated each time the count direction of
T3 changes. In Edge Detection Mode (T3M = 111_B), an interrupt request is generated
each time a count edge for T3 is detected. Count direction, changes in the count
direction, and count requests are monitored by status bits T3RDIR, T3CHDIR, and
T3EDGE in register T3CON.
User’s Manual
GPT_X41, V2.0
14-11
V2.1, 2004-03