XC164-16 Datasheet, PDF (199/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Capture/Compare Unit 6 (CAPCOM6)
The capturing of the timer value in register CC60R, the shadow transfer from registers
CC61SR to CC61R, from CC62SR to CC62R, and for the T12 period value, is done
together with the reset event for T12.
18.5.4 Hall Mode Flags
Depending on the Hall pattern compare operation, a number of flags are set in order to
indicate the status of the module and to trigger further actions and interrupt requests.
Flag CHE (Correct Hall Event) in register IS is set via signal CM_CHE when the sampled
Hall pattern matches the expected one (EXPH). This flag can also be set by SW via
setting bit SCHE in register ISS. If enabled through bit ENCHE (in register IEN), the set
signal for CHE can also generate an interrupt request to the CPU. To clear flag CHE, SW
needs to write a 1 to bit RCHE in register ISR.
Flag WHE indicates a Wrong Hall Event. Its handling for flag setting and resetting as well
as interrupt request generation is the same as described above for flag CHE.
The implementation of flag STR is done in the same way as for CHE and WHE. This flag
is set by HW via the shadow transfer signal MCM_ST (see also Figure 18-31).
User’s Manual
CAPCOM6_X, V2.0
18-55
V2.1, 2004-03