XC164-16 Datasheet, PDF (60/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
Count
Clock
CAPIN
T3IN
T3EUD
Edge
Select
0
MUX
1
Signal
Select
CT3
CI
Auxiliary
Timer T5
Clear
Up/Down
T5CLR
Capture
Capture
Correction
T5CC
T5SC
CAPREL
Register
T5IRQ
CRIRQ
T6CLR
Clear
T6
MCA05410
Figure 14-29 GPT2 Register CAPREL in Capture Mode
When a selected trigger is detected, the contents of the auxiliary timer T5 are latched
into register CAPREL and the interrupt request line CRIRQ is activated. The same event
can optionally clear timer T5 and/or timer T6. This option is enabled by bit T5CLR in
register T5CON and bit T6CLR in register T6CON, respectively. If TxCLR = 0 the
contents of timer Tx is not affected by a capture. If TxCLR = 1 timer Tx is cleared after
the current timer T5 value has been latched into register CAPREL.
Note: Bit T5SC only controls whether or not a capture is performed. If T5SC is cleared
the external input pin(s) can still be used to clear timer T5 and/or T6, or as external
interrupt input(s). This interrupt is controlled by the CAPREL interrupt control
register CRIC.
When capture triggers T3IN or T3EUD are enabled (CT3 = 1), register CAPREL captures
the contents of T5 upon transitions of the selected input(s). These values can be used
to measure T3’s input signals. This is useful, for example, when T3 operates in
User’s Manual
GPT_X41, V2.0
14-47
V2.1, 2004-03