XC164-16 Datasheet, PDF (51/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
Gated Timer Mode
Gated timer mode for the core timer T6 is selected by setting bitfield T6M in register
T6CON to 010_B or 011_B. Bit T6M.0 (T6CON.3) selects the active level of the gate input.
The same options for the input frequency are available in gated timer mode as in timer
mode (see Section 14.2.6). However, the input clock to the timer in this mode is gated
by the external input pin T6IN (Timer T6 External Input).
To enable this operation, the associated pin T6IN must be configured as input (the
corresponding direction control bit must contain 0).
f
GPT
T6IN
Prescaler
BPS2 T6I
T6UD
T6EUD
f
Gate ^T6
Ctrl.
Count
Core Timer T6
T6R
Clear
0
MUX
Up/Down
=1
1
T6UDE
Toggle Latch
T6IRQ
T6OUT
to T5,
CAPREL
T6OUF
MCB05404_X4
Figure 14-23 Block Diagram of Core Timer T6 in Gated Timer Mode
If T6M = 010_B, the timer is enabled when T6IN shows a low level. A high level at this line
stops the timer. If T6M = 011_B, line T6IN must have a high level in order to enable the
timer. Additionally, the timer can be turned on or off by software using bit T6R. The timer
will only run if T6R is 1 and the gate is active. It will stop if either T6R is 0 or the gate is
inactive.
Note: A transition of the gate signal at pin T6IN does not cause an interrupt request.
User’s Manual
GPT_X41, V2.0
14-38
V2.1, 2004-03