XC164-16 Datasheet, PDF (68/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
14.2.8 Interrupt Control for GPT2 Timers and CAPREL
When a timer overflows from FFFF_H to 0000_H (when counting up), or when it underflows
from 0000_H to FFFF_H (when counting down), its interrupt request flag (T5IR or T6IR) in
register TxIC will be set. Whenever a transition according to the selection in bit field CI
is detected at pin CAPIN, interrupt request flag CRIR in register CRIC is set. Setting any
request flag will cause an interrupt to the respective timer or CAPREL interrupt vector
(T5INT, T6INT or CRINT) or trigger a PEC service, if the respective interrupt enable bit
(T5IE or T6IE in register TxIC, CRIE in register CRIC) is set. There is an interrupt control
register for each of the two timers and for the CAPREL register.
GPT12E_T5IC
Timer 5 Intr. Ctrl. Reg.
SFR (FF66_H/B3_H)
15 14 13 12 11 10 9 8 7 6 5
- - - - - - - GPX T5IR T5IE
- - - - - - - rw rwh rw
Reset Value: - - 00_H
43210
ILVL
rw
GLVL
rw
GPT12E_T6IC
Timer 6 Intr. Ctrl. Reg.
SFR (FF68_H/B4_H)
15 14 13 12 11 10 9 8 7 6 5
- - - - - - - GPX T6IR T6IE
- - - - - - - rw rwh rw
Reset Value: - - 00_H
43210
ILVL
GLVL
rw
rw
GPT12E_CRIC
CAPREL Intr. Ctrl. Reg.
SFR (FF6A_H/B5_H)
Reset Value: - - 00_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- - - - - - - GPX CRIR CRIE
ILVL
GLVL
- - - - - - - rw rwh rw
rw
rw
Note: Please refer to the general Interrupt Control Register description for an
explanation of the control fields.
User’s Manual
GPT_X41, V2.0
14-55
V2.1, 2004-03