XC164-16 Datasheet, PDF(53/417 Page) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

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XC164-16 Datasheet, PDF (53/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

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XC164-16 Derivatives

Peripheral Units (Vol. 2 of 2)

The General Purpose Timer Units

14.2.3 GPT2 Auxiliary Timer T5 Control

Auxiliary timer T5 can be configured for timer mode, gated timer mode, or counter mode

with the same options for the timer frequencies and the count signal as the core timer

T6. In addition to these 3 counting modes, the auxiliary timer can be concatenated with

the core timer. The contents of T5 may be captured to register CAPREL upon an external

or an internal trigger. The start/stop function of the auxiliary timers can be remotely

controlled by the T6 run control bit. Several timers may thus be controlled synchronously.

The current contents of the auxiliary timer are reflected by its count register T5. This

register can also be written to by the CPU, for example, to set the initial start value.

The individual configurations for timer T5 are determined by its bitaddressable control

register T5CON. Some bits in this register also control the function of the CAPREL

register. Note that functions which are present in all timers of block GPT2 are controlled

in the same bit positions and in the same manner in each of the specific control registers.

Note: The auxiliary timer has no output toggle latch and no alternate output function.

GPT12E_T5CON

Timer 5 Control Register

SFR (FF46H/A3H)

Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

T5 T5

SC CLR

CI

T5

CC

CT3

T5

RC

T5

UDE

T5

UD

T5R

T5M

T5I

rw rw

rw

rw rw rw rw rw rw

rw

rw

Field

T5SC

T5CLR

CI

Bits Type

15

rw

14

rw

[13:12] rw

Description

Timer 5 Capture Mode Enable

0 Capture into register CAPREL Disabled

1 Capture into register CAPREL Enabled

Timer T5 Clear Enable Bit

0 Timer T5 is not cleared on a capture event

1 Timer T5 is cleared on a capture event

Register CAPREL Capture Trigger Selection

(depending on bit CT3)

00 Capture disabled

01 Positive transition (rising edge) on CAPIN or

any transition on T3IN

10 Negative transition (falling edge) on CAPIN or

any transition on T3EUD

11 Any transition (rising or falling edge) on CAPIN

or any transition on T3IN or T3EUD

Userâs Manual

GPT_X41, V2.0

14-40

V2.1, 2004-03

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