XC164-16 Datasheet, PDF (371/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
TwinCAN Module
The control and status element of the message control registers is implemented with two
complementary bits (except the frame counter value). This special mechanism allows
the selective setting or resetting of a specific element (leaving others unchanged) without
requiring read-modify-write cycles. Table 21-8 illustrates how to use these 2-bitfields.
Table 21-8 Setting/Resetting the Control and Status Element of the Message
Control Registers
Value of
Function on Write
the 2-bitfield
Meaning on Read
00_B
reserved
reserved
01_B
Reset element
Element is reset
10_B
Set element
Element is set
11_B
Leave element unchanged
reserved
Register MSGCFGn defines the configuration of message object n and the associated
interrupt node pointers. Changes of bits XTD, NODE or DIR by software are only taken
into account after setting bitfield MSGVAL to ‘10’. This avoids unintentional modification
while the message object is still active by explicitly defining a timing instant for the
update. Bits XTD, NODE or DIR can be written while MSGVAL is ‘01’ or ‘10’, the update
always takes place by setting MSGVAL to ‘10’.
MSGCFGHn (n = 31-0)
Message Object n Message Configuration Register High
MSGCFGLn (n = 31-0)
Message Object n Message Configuration Register Low
15 14 13 12 11 10 9 8 7 6 5 4
Reset Value: 0000_H
Reset Value: 0000_H
3210
0
TXINP
0
RXINP
r
rw
r
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
DLC
DIR
XTD
NO
DE
RMM
r
rwh
rwh rw rwh rw
User’s Manual
TwinCAN_X41, V2.1
21-71
V2.1, 2004-03