XC164-16 Datasheet, PDF (114/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Capture/Compare Units
17.2
CAPCOM Timer Interrupts
Upon a timer overflow the corresponding timer interrupt request flag TxIR for the
respective timer will be set. This flag can be used to generate an interrupt or trigger a
PEC service request, when enabled by the respective interrupt enable bit TxIE.
Each timer has its own bitaddressable interrupt control register and its own interrupt
vector. The organization of the interrupt control registers TxIC is identical with the other
interrupt control registers.
CC1_T0IC
CAPCOM T0 Intr. Ctrl. Reg.
SFR (FF9C_H/CE_H)
15 14 13 12 11 10 9 8 7 6 5
-
GPX T0IR T0IE
- - - - - - - rw rwh rw
Reset Value: - - 00_H
43210
ILVL
rw
GLVL
rw
CC1_T1IC
CAPCOM T1 Intr. Ctrl. Reg.
SFR (FF9E_H/CF_H)
15 14 13 12 11 10 9 8 7 6 5
-
GPX T1IR T1IE
- - - - - - - rw rwh rw
Reset Value: - - 00_H
43210
ILVL
rw
GLVL
rw
CC2_T7IC
CAPCOM T7 Intr. Ctrl. Reg.
ESFR (F17A_H/BE_H)
15 14 13 12 11 10 9 8 7 6 5
-
GPX T7IR T7IE
- - - - - - - rw rwh rw
Reset Value: - - 00_H
43210
ILVL
rw
GLVL
rw
CC2_T8IC
CAPCOM T8 Intr. Ctrl. Reg.
ESFR (F17C_H/BF_H)
15 14 13 12 11 10 9 8 7 6 5
Reset Value: - - 00_H
43210
-
GPX T8IR T8IE
ILVL
GLVL
- - - - - - - rw rwh rw
rw
rw
Note: Please refer to the general Interrupt Control Register description for an
explanation of the control fields.
User’s Manual
CC12_X41, V2.1
17-9
V2.1, 2004-03