XC164-16 Datasheet, PDF (377/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

Field
FD
SDT
STT
XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
TwinCAN Module
Bits Type Description
13
rw
Low
FIFO Direction
FD is only taken into account for a FIFO base object (the
FD bits of all FIFO elements should have an identical
value). It defines which transfer action (reception or
transmission) leads to an update of the FIFO base
object’s CANPTR.
0 FIFO Reception: The CANPTR (of the FIFO base
object) is updated after a correct reception of a
data frame (DIR = ‘0’) or a remote frame (DIR = ‘1’)
by the currently addressed message object. The
CANPTR is left unchanged after any transmission.
1 FIFO Transmission: The CANPTR (of the FIFO
base object) is updated after a correct
transmission of a data frame (DIR = ‘1’) or a
remote frame (DIR = ‘0’) from the currently
addressed message object. The CANPTR is left
unchanged after any reception.
Bitfield FD is not correlated with bit DIR.
14
rw
Low
Single Data Transfer Mode
This bit is taken into account in any transfer mode (FIFO
mode or as standard object, receive and transmit
objects).
0 Control bit MSGVAL is not reset when this object
has taken part in a successful data transfer
(receive or transmit).
1 Control bit MSGVAL is automatically reset after a
successful data transfer (receive or transmit) has
taken place.
Bit SDT is not taken into account for remote frames.
Bit SDT has to be reset in all message objects belonging
to a FIFO buffer.
15
rw
Low
Single Transmission Try
0 Single transmission try is disabled.
1 Single transmission try is enabled. The
corresponding TXRQ bit is reset immediately after
the transmission has started¹⁾.
User’s Manual
TwinCAN_X41, V2.1
21-77
V2.1, 2004-03