XC164-16 Datasheet, PDF (215/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Capture/Compare Unit 6 (CAPCOM6)
18.9
Interrupt Generation
The interrupt structure is shown in Figure 18-44. The HW interrupt event or the SW
setting of the corresponding interrupt set bit (in register ISS) can trigger the interrupt
generation. The interrupt pulse is generated independently from the interrupt flag in
register IS. The interrupt flag can be reset by SW by writing to the corresponding bit in
register ISR.
If enabled by the related interrupt enable bit in register IEN, an interrupt pulse can be
generated on one of the four interrupt output lines, I0 … I3, of the module. If more than
one interrupt source is connected to the same interrupt node pointer (in register INP), the
requests are combined to one common line.
CC60 Cap./Com. Rising
CC60 Cap./Com. Falling
CC61 Cap./Com. Rising
CC61 Cap./Com. Falling
CC62 Cap./Com. Rising
CC62 Cap./Com. Falling
T12 One-Match
T12 Period-Match
T13 Compare-Match
T13 Period-Match
Correct Hall Event
MCM Shadow Transfer
Trap Condition
Wrong Hall Event
Interrupt Enable Interrupt Status
Register IEN
Register IS
16
16
I0
I1
I2
I3
Interrupt Control Logic
14
16
Interrupt Set
Register ISS
16
Interrupt Reset
Register ISR
CC6_INT
CC6_EINT
CC6_T12INT
CC6_T13INT
Node Pointer
Register INP
MCA05548
Figure 18-44 Interrupt Structure Overview
User’s Manual
CAPCOM6_X, V2.0
18-71
V2.1, 2004-03