XC164-16 Datasheet, PDF (81/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Real Time Clock
15.4
RTC Interrupt Generation
The overflow signals of each timer of the RTC timer chain can generate an interrupt
request. The RTC’s interrupt subnode control register ISNC combines these requests to
activate the common RTC interrupt request line RTC_IRQ.
Each timer overflow sets its associated request flag in register ISNC. Individual enable
bits for each request flag determine whether this request also activates the common
interrupt line. The enabled requests are ORed together on this line (see Figure 15-5).
The interrupt handler can determine the source of an interrupt request via the specific
request flags and must clear them after appropriate processing (not cleared by
hardware). The common node request bit is automatically cleared when the interrupt
handler is vectored to.
Note: If only one source is enabled, no additional software check is required, of course.
Both the individual request and the common interrupt node must be enabled.
Register RTC_ISNC
Set
CNT3 Overflow
CNT3
IR
&
SW Clear
CNT3
IE
Set
CNT2 Overflow
CNT2
IR
&
SW Clear
CNT2
IE
Set
CNT1 Overflow
CNT1
IR
&
SW Clear
CNT1
IE
Set
CNT0 Overflow
CNT0
IR
&
SW Clear
CNT0
IE
Set
T14 Overflow
T14
IR
&
SW Clear
T14
IE
Figure 15-5 Interrupt Block Diagram
>^_ 1
Interrupt Request
RTC_IRQ
MCB05415
User’s Manual
RTC_X41, V2.1
15-12
V2.1, 2004-03