XC164-16 Datasheet, PDF (289/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
High-Speed Synchronous Serial Interface (SSC)
The shift register of the SSC is connected to both, the transmit lines and the receive lines
via the pin control logic (see block diagram in Figure 20-2). Transmission and reception
of serial data are synchronized and take place at the same time, i.e. the same number
of transmitted bits is also received.
To prepare for a transfer, the transmit data is written into the Transmit Buffer (SSCx_TB)
by software. It is moved to the shift register as soon as this is empty. An SSC master
(CON.MS = 1) immediately begins transmitting, while an SSC slave (CON.MS = 0) will
wait for an active shift clock. When the transfer starts, the busy flag CON.BSY is set and
the Transmit Interrupt Request line TIRQ will be activated to indicate that register
SSCx_TB may be reloaded again. When the programmed number of bits (2 … 16) has
been transferred, the contents of the shift register are moved to the Receive Buffer
SSCx_RB and the Receive Interrupt Request line RIRQ is activated. If no further transfer
is to take place (SSCx_TB is empty), CON.BSY will be cleared at the same time.
Software should not modify CON.BSY, as this flag is hardware controlled.
Note: Only one SSC can be master at a given time in a serial system.
The transfer of serial data bits can be programmed in many respects:
• The data width can be specified from 2 bits to 16 bits
• A transfer may start with either the LSB or the MSB
• The shift clock may be idle low or idle high
• The data bits may be shifted with the leading edge or the trailing edge of the shift
clock signal
• The baudrate may be set from 306.6 bit/s up to 20 Mbit/s (@ 40 MHz module clock)
• The shift clock can be generated (MSCLK) or can be received (SSCLK)
These features allow the adaptation of the SSC to a wide range of applications in which
serial data transfer is required.
The Data Width Selection supports the transfer of frames of any data length, from 2-bit
“characters” up to 16-bit “characters”. Starting with the LSB (CON.HB = 0) enables
communication with SSC devices in Synchronous Mode or with 8051-like serial
interfaces, for example. Starting with the MSB (CON.HB = 1) enables operation
compatible with the SPI interface.
Regardless of the data width selected and whether the MSB or the LSB is transmitted
first, the transfer data is always right-aligned in registers SSCx_TB and SSCx_RB, with
the LSB of the transfer data in bit 0 of these registers. The data bits are rearranged for
transfer by the internal shift register logic. The unselected bits of SSCx_TB are ignored;
the unselected bits of SSCx_RB will not be valid and should be ignored by the receiver
service routine.
The Clock Control allows the adaptation of transmit and receive behavior of the SSC to
a variety of serial interfaces. A specific shift clock edge (rising or falling) is used to shift
out transmit data, while the other shift clock edge is used to latch in receive data. Bit PH
selects the leading edge or the trailing edge for each function. Bit PO selects the level of
User’s Manual
SSC_X, V2.0
20-7
V2.1, 2004-03