XC164-16 Datasheet, PDF (66/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
External Count Clock Input
The external input signals of the GPT2 block are sampled with the GPT2 basic clock (see
Figure 14-20). To ensure that a signal is recognized correctly, its current level (high or
low) must be held active for at least one complete sampling period, before changing. A
signal transition is recognized if two subsequent samples of the input signal represent
different levels. Therefore, a minimum of two basic clock periods are required for the
sampling of an external input signal. Thus, the maximum frequency of an input signal
must not be higher than half the basic clock.
Table 14-18 summarizes the resulting requirements for external GPT2 input signals.
Table 14-18 GPT2 External Input Signal Limits
System Clock = 10 MHz Input
Max. Input Min. Level ^Frequ.
Frequency Hold Time ^Factor
GPT2 Input
System Clock = 40 MHz
Divider Phase _{Max. Input Min. Level}
BPS1 Duration _{Frequency Hold Time}
2.5 MHz
1.25 MHz
625.0 kHz
312.5 kHz
200 ns
400 ns
800 ns
1.6 µs
f_GPT/4
01_B
f_GPT/8
00_B
f_GPT/16 11_B
f_GPT/32 10_B
2 × t_GPT
4 × t_GPT
8 × t_GPT
16 × t_GPT
10.0 MHz
5.0 MHz
2.5 MHz
1.25 MHz
50 ns
100 ns
200 ns
400 ns
These limitations are valid for all external input signals to GPT2, including the external
count signals in counter mode and the gate input signals in gated timer mode.
User’s Manual
GPT_X41, V2.0
14-53
V2.1, 2004-03