XC164-16 Datasheet, PDF (45/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
space (see Section 14.2.7). When any of the timer registers is written to by the CPU in
the state immediately preceding a timer increment, decrement, reload, or capture
operation, the CPU write operation has priority in order to guarantee correct results.
The interrupts of GPT2 are controlled through the Interrupt Control Registers TxIC.
These registers are not part of the GPT2 block. The input and output lines of GPT2 are
connected to pins of Ports P3 and P5. The control registers for the port functions are
located in the respective port modules.
Note: The timing requirements for external input signals can be found in Section 14.2.6,
Section 14.3 summarizes the module interface signals, including pins.
f _GPT
T5IN
T5EUD
2ⁿ: 1
T6CON.BPS2
T5
Mode
Control
Basic clock
GPT2 Timer T5
U/D
Clear
Interrupt
Request
(T5IR)
CAPIN
T3IN/
T3EUD
T6IN
T6EUD
CAPREL
Mode
Control
T6
Mode
Control
Capture
GPT2 CAPREL
Reload
Clear
GPT2 Timer T6
U/D
Figure 14-20 GPT2 Block Diagram
User’s Manual
GPT_X41, V2.0
14-32
Toggle FF
T6OTL
Interrupt
Request
(CRIR)
Interrupt
Request
(T6IR)
T6OUT
T6OUF
mc_gpt0108_bldiax4.vsd
V2.1, 2004-03