XC164-16 Datasheet, PDF (22/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
Gated Timer Mode
Gated timer mode for the core timer T3 is selected by setting bitfield T3M in register
T3CON to 010_B or 011_B. Bit T3M.0 (T3CON.3) selects the active level of the gate input.
The same options for the input frequency are available in gated timer mode as in timer
mode (see Section 14.1.5). However, the input clock to the timer in this mode is gated
by the external input pin T3IN (Timer T3 External Input).
To enable this operation, the associated pin T3IN must be configured as input, that is,
the corresponding direction control bit must contain 0.
f
GPT
T3IN
Prescaler
BPS1 T3I
T3UD
T3EUD
f
Gate ^T3
Ctrl.
Count
Core Timer T3
T3R
0
MUX _Up/Down
=1
1
T3UDE
Toggle Latch
T3IRQ
T3OUT
to
T2/T4
MCB05392
Figure 14-5 Block Diagram of Core Timer T3 in Gated Timer Mode
If T3M = 010_B, the timer is enabled when T3IN shows a low level. A high level at this line
stops the timer. If T3M = 011_B, line T3IN must have a high level in order to enable the
timer. Additionally, the timer can be turned on or off by software using bit T3R. The timer
will only run if T3R is 1 and the gate is active. It will stop if either T3R is 0 or the gate is
inactive.
Note: A transition of the gate signal at pin T3IN does not cause an interrupt request.
User’s Manual
GPT_X41, V2.0
14-9
V2.1, 2004-03