XC164-16 Datasheet, PDF (123/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Capture/Compare Units
17.5.3 Compare Mode 2
Compare mode 2 is an interrupt-only mode similar to compare mode 0. The main
difference is that only one compare match, corresponding to one interrupt request, is
possible within a given timer period.
when a match is detected in compare mode 2 for the first time within a count period of
the allocated timer, the interrupt request line CCyIRQ is activated. In addition, all further
compare matches within the current timer period are disabled, even if a new compare
value, higher than the current timer contents, would be written to the register. This
blocking is only released when the allocated timer overflows. A new compare value
written to the compare register after the first match will only go into effect within the
following timer period.
17.5.4 Compare Mode 3
Compare mode 3 is based on compare mode 2, but additionally influences the
associated port pin. Only one compare event is possible within one timer period.
When a match is detected in compare mode 3 for the first time within a count period of
the allocated timer, the interrupt request line CCyIRQ is activated, and the associated
output signal is set to 1. In addition, all further compare matches within the current timer
period are disabled, even if a new compare value, higher than the current timer contents,
would be written to the register. This blocking is only released when the allocated timer
overflows. A new compare value written to the compare register after the first match will
only go into effect within the following timer period.
The overflow signal is also used to reset the associated output signal to 0.
Special attention has to be paid when the compare value is set equal to the timer reload
value. In this case, the compare match signal would try to set the output signal, while the
timer overflow tries to reset the output signal. This conflict is avoided such that the state
of the output signal is left unchanged in this case.
Note: When the compare value is changed from a value above the current timer
contents to a value below the current timer contents, the new value is not
recognized before the next timer period.
For the exact operation of the port output signal, please see Section 17.6.
User’s Manual
CC12_X41, V2.1
17-18
V2.1, 2004-03