XC164-16 Datasheet, PDF (52/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
Counter Mode
Counter mode for the core timer T6 is selected by setting bitfield T6M in register T6CON
to 001_B. In counter mode, timer T6 is clocked by a transition at the external input pin
T6IN. The event causing an increment or decrement of the timer can be a positive, a
negative, or both a positive and a negative transition at this line. Bitfield T6I in control
register T6CON selects the triggering transition (see Table 14-12).
T6IN
Edge
Select
Count
Core Timer T6
T6UD
T6EUD
T6R
T6I
Clear
0
MUX _Up/Down
=1
1
T6UDE
Toggle Latch
T6IRQ
T6OUT
to T5,
CAPREL
T6OUF
MCB05405_X4
Figure 14-24 Block Diagram of Core Timer T6 in Counter Mode
Table 14-12 GPT2 Core Timer T6 (Counter Mode) Input Edge Selection
T6I
Triggering Edge for Counter Increment/Decrement
000
None. Counter T6 is disabled
001
Positive transition (rising edge) on T6IN
010
Negative transition (falling edge) on T6IN
011
Any transition (rising or falling edge) on T6IN
1XX
Reserved. Do not use this combination
For counter mode operation, pin T6IN must be configured as input (the respective
direction control bit DPx.y must be 0). The maximum input frequency allowed in counter
mode depends on the selected prescaler value. To ensure that a transition of the count
input signal applied to T6IN is recognized correctly, its level must be held high or low for
a minimum number of module clock cycles before it changes. This information can be
found in Section 14.2.6.
User’s Manual
GPT_X41, V2.0
14-39
V2.1, 2004-03