XC164-16 Datasheet, PDF (202/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

Field
STRMCM
MCMPS
XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Capture/Compare Unit 6 (CAPCOM6)
Bits Type Description
7
w
Shadow Transfer Request for MCMPS
Setting this bit during a write action leads to an
immediate update of bitfield MCMP by the value
written to MCMPS. This functionality permits an
update triggered by SW. When read, this bit always
delivers 0.
0 MCMP is updated according to the defined HW
action. The write access to MCMPS does not
modify MCMP.
1 MCMP is updated by the value written to
MCMPS.
[5:0] rw
Multi-Channel PWM Pattern Shadow Field
MCMPS is the shadow field for bitfield MCMP. The
Multi-Channel shadow transfer is triggered according
to the transfer conditions defined by register
MCMCTR.
Register MCMOUT holds the Modulation and Hall patterns that are currently used.
CCU6_MCMOUT
Multi-Ch. Mode Output Reg.
XSFR (E8CC_H/--)
Reset Value: 0000_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
--
--
CURH
rh
EXPH
rh
-R
- rh
MCMP
rh
Field
CURH¹⁾
Bits Type
[13:11] rh
Description
Current Hall Pattern
CURH is written by a shadow transfer from bitfield
CURHS. Bitfield CURH is compared to the sampled
Hall pattern after every detected edge at the Hall
sensor inputs CC6POSx. If the pattern match, the
detected edge has been an invalid transition (e.g.
due to a spike), and no further action is performed. If
the sampled pattern do not either match CURH or
EXPH, a Wrong Hall Event signal is set, which can
trigger further actions.
User’s Manual
CAPCOM6_X, V2.0
18-58
V2.1, 2004-03