XC164-16 Datasheet, PDF (165/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Capture/Compare Unit 6 (CAPCOM6)
18.1.3 Dead-Time Generation
The generation of (complementary) signals for the highside and the lowside switches of
one power inverter phase is based on the same compare channel. For example, if the
highside switch should be active while the T12 counter value is above the compare value
(State Bit = 1), then the lowside switch should be active while the counter value is below
the compare value (State Bit = 0).
In most cases, the switching behavior of the connected power switches is not
symmetrical concerning the switch-on and switch-off times. A general problem arises if
the time for switch-on is smaller than the time for switch-off of the power device. In this
case, a short-circuit can occur in the inverter bridge leg, which may damage the
complete system. In order to solve this problem by HW, this capture/compare unit
contains a programmable Dead-Time Generation Block, which is able to delay the
passive to active edge of the switching signals (the active to passive edge is not
delayed).
The Dead-Time Generation Block, illustrated in Figure 18-16, is built in a similar way for
all three channels of T12. Any change of a CC6xST bit triggers the corresponding Dead-
Time Counter, a single-shot 6-bit down counter which is clocked with the same input
clock as T12 (f_T12). A trigger pulse DTCx_IN, activated by the change of the State Bit
CC6xST, leads to a reload of the dead-time counter with the value DTM stored in register
T12DTC and starts the counter.
Reload Value
DTM
DTC0_IN
&
DTE0
DTC1_IN
&
DTE1
DTC2_IN
&
DTE2
f
T12
DTRES
6-bit
Down Counter
6-bit
Down Counter
Figure 18-16 Dead-Time Generation Block Diagram
6-bit
Down Counter
DTR2
DTR1
DTR0
MCB05520
User’s Manual
CAPCOM6_X, V2.0
18-21
V2.1, 2004-03