XC164-16 Datasheet, PDF (249/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Asynchronous/Synchronous Serial Interface (ASC)
Table 19-3 Asynchronous Baudrate Formulas Using the Fixed Input Clock
Dividers
FDE
BRS
BG
Formula
0
0
0 … 8191 _{Baudrate = -------------f--A---S---C---------------}
32 × (BG + 1)
BG = ---------------^f--^A---^S---^C---------------- – 1
32 × Baudrate
1
Baudrate = -------------^f--^A---^S---^C---------------
48 × (BG + 1)
BG = ---------------^f--^A---^S---^C---------------- – 1
48 × Baudrate
Table 19-4
Baudrate
1.25 Mbit/s
19.2 kbit/s
9600 bit/s
4800 bit/s
2400 bit/s
1200 bit/s
Typical Asynchronous Baudrates Using the Fixed Input Clock
Dividers
BRS = 0, f_ASC = 40 MHz
BRS = 1, f_ASC = 40 MHz
Deviation Error Reload Value Deviation Error Reload Value
---
+0.1% / -1.3%
+0.1% / -0.6%
+0.1% / -0.2%
+0.1% / -0.0%
+0.0% / -0.0%
0000_H
0040_H / 0041_H
0081_H / 0082_H
0103_H / 0104_H
0207_H / 0208_H
0410_H / 0411_H
NA
+0.9% / -1.3%
+0.9% / -0.2%
+0.3% / -0.2%
+0.0% / -0.2%
+0.0% / -0.0%
NA
002A_H / 002B_H
0055_H / 0056_H
00AC_H / 00AD_H
015A_H / 015B_H
02B5_H / 02B6_H
Using the Fractional Divider
When the fractional divider is selected, the input clock f_DIV for the baudrate timer is
derived from the module clock f_ASC by a programmable divider. If bit FDE is set, the
fractional divider is activated. It divides f_ASC by a fraction of n/512 for any value of n from
0 to 511. If n = 0, the divider ratio is 1, which means that f_DIV = f_ASC. In general, the
fractional divider allows the baudrate to be programmed with much more accuracy than
with the two fixed prescaler divider stages.
Note: BG represents the contents of the reload bitfield BR_VALUE, taken as an
unsigned 13-bit integer.
Note: FDV represents the contents of the fractional divider register FD_VALUE taken as
an unsigned 9-bit integer.
User’s Manual
ASC_X, V2.0
19-24
V2.1, 2004-03