XC164-16 Datasheet, PDF (238/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Asynchronous/Synchronous Serial Interface (ASC)
The receive FIFO cannot be accessed directly. All data read operations from the
RXFIFO are executed by reading the RBUF register.
RXFCON.RXFITL = 0011_B
Content of
FSTAT.RXFFL
0000
Byte 1
0001
Byte 2
Byte 1
0010
Byte 3
Byte 2
Byte 1
0011
Byte 4
Byte 3
Byte 2
Byte 1
Byte 4
Byte 5
Byte 4
0100
0001
0010
Byte 6
Byte 5
Byte 4
RXFIFO
Empty
0100 0000
RxD Byte 1
Byte 2
Byte 3
Byte 4
RIR
RIR
Byte 5
Byte 6
RIR
Read RBUF (Byte 1)
Read RBUF (Byte 2)
Read RBUF (Byte 3)
Read RBUF (Byte 4)
Read RBUF (Byte 5)
Read RBUF (Byte 6)
MCT05439
Figure 19-8 Receive FIFO Operation Example
The example in Figure 19-8 shows a typical 8-stage receive FIFO operation. In this
example, six bytes are received via the RxD input line. The receive FIFO interrupt trigger
level RXFITL is set to 0011_B. Therefore, the first receive interrupt RIR is generated after
the reception of byte 3 (RXFIFO is filled with three bytes).
After the reception of byte 4, three bytes are read out of the receive FIFO. After this read
operation, the RXFIFO still contains one byte. RIR becomes again active after two more
bytes (byte 5 and 6) have been received (RXFIFO filled again with 3 bytes). Finally, the
FIFO is cleared after three read operation.
If the RXFIFO is full and additional bytes are received, the receive interrupt RIR and the
error interrupt EIR will be generated with bit OE set. In this case, the data byte last written
into the receive FIFO is overwritten. With the overrun condition, the receive FIFO filling
level RXFFL is set to maximum. If a RBUF read operation is executed with the RXFIFO
User’s Manual
ASC_X, V2.0
19-13
V2.1, 2004-03