XC164-16 Datasheet, PDF (205/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Capture/Compare Unit 6 (CAPCOM6)
18.6
Trap Handling
The trap functionality permits the PWM outputs to react on the state of the input pin
CTRAP. This functionality can be used to switch off the power devices if the trap input
becomes active (e.g. to perform an emergency stop).
The Trap Flag TRPF monitors the trap input and initiates the entry into the Trap State. It
can also be set by SW. The Trap State Bit TRPS determines the effect on the outputs
and controls the exit of the Trap State.
When a trap condition is detected, both, the Trap Flag TRPF and the Trap State Bit
TRPS, are set to 1. The Trap State is entered immediately. The output of the Trap State
Bit TRPS leads to the Output Modulation Block and can there deactivate the outputs (set
them to the passive state). Individual enable control bits for each of the six T12-related
outputs and the T13-related output facilitate a flexible adaptation to the application needs
(see Section 18.7).
There are a number of different ways to exit the Trap State. This offers SW the option to
select the operation which is best for the given application. Exiting the Trap State can be
done either immediately when the trap condition is removed, or under software control,
or synchronously to the PWM generated by either Timer T12 or Timer T13.
Figure 18-37 gives an overview on the trap function. Both, the Trap Flag TRPF and the
Trap State Bit TRPS, located in register IS, are set to 1 when input CTRAP is activated.
The Trap Flag TRPF can also be set by SW via bit STRPF. In turn, the Trap State Bit
TRPS will also be set through its Set/Reset Control block. As long as pin CTRAP = 0,
TRPF and TRPS remain set and can not be cleared (assuming TRPPEN = 1).
CTRAP
TRPPEN
T12_ZM
T13_ZM
STRPF RTRPF
Set/Reset
Control
Set
Reset
Reg. IS
Trap
Flag
TRPF
TRPM2
Set/Reset
Control
Set
Reset
Reg. IS
Trap
State
TRPS
TRPM1 TRPM0
Figure 18-37 Trap Logic Block Diagram
To Output
Modulation
MCB05541
User’s Manual
CAPCOM6_X, V2.0
18-61
V2.1, 2004-03