XC164-16 Datasheet, PDF (329/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
TwinCAN Module
To FIFO
Object n
To FIFO
To FIFO
To FIFO
Object n + 1 Object n + 2 Object n + 3
Message 1 Message 2 Message 3 Message 4
Source Bus
Speed A
Node A
TwinCAN
Node B
Destination Bus
Speed B
Message 1 Message 2 Message 3 Message 4
To FIFO
Object n
To FIFO
Object n + 1
To FIFO
Object n + 2
To FIFO
Object n + 3
MCA05486
Figure 21-16 Message Burst in Case of FIFO/Gateway
21.1.6.1 Normal Gateway Mode
The normal gateway mode consumes two message objects to transfer a message from
the source to the destination node. In this mode, different identifiers can be used for the
same message data. Details of the message transfer through the normal gateway are
controlled by the respective MSGFGCR_<s> and MSGFGCR_<d> registers. All 8 data bytes
from the source object (even if not all bytes are valid) are copied to the destination object.
The object receiving the information from the source node has to be configured as
receive message object (DIR = 0) and must be associated to the source CAN bus via bit
NODE. Register MSGFGCR_<s> should be initialized according the following
enumeration:
• Bitfield MMC_<s> has to be set to ‘100’ indicating a normal mode gateway for incoming
(data) frames.
• Bitfield CANPTR_<s> must be initialized with the number of the message object used
as destination for the data copy process.
• If no FIFO functionality is required on the destination side, bitfield FSIZE_<s> has to be
filled with ‘00000’. When FIFO capabilities are needed, bitfield FSIZE_<s> must contain
the FIFO buffer length, which has to be identical with the content of the FIFO base
object’s FSIZE bitfield on the destination side.
User’s Manual
TwinCAN_X41, V2.1
21-29
V2.1, 2004-03