XC164-16 Datasheet, PDF (100/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
The Analog/Digital Converter
16.4
Conversion Timing Control
When a conversion is started, first the capacitances of the converter are loaded via the
respective analog input pin to the current analog input voltage. The time to load the
capacitances is referred to as sample time. Next the sampled voltage is converted to a
digital value in successive steps, which correspond to the resolution of the ADC. During
these phases (except for the sample time) the internal capacitances are repeatedly
charged and discharged via pins V_AREF and V_AGND.
The current that has to be drawn from the sources for sampling and changing charges
depends on the time that each respective step takes, because the capacitors must reach
their final voltage level within the given time, at least with a certain approximation. The
maximum current, however, that a source can deliver, depends on its internal resistance.
The time that the two different actions during conversion take (sampling, and converting)
can be programmed within a certain range in the XC164 relative to the CPU clock. The
absolute time that is consumed by the different conversion steps therefore is
independent from the general speed of the controller. This allows adjusting the A/D
converter of the XC164 to the properties of the system:
Fast Conversion can be achieved by programming the respective times to their
absolute possible minimum. This is preferable for scanning high frequency signals. The
internal resistance of analog source and analog supply must be sufficiently low,
however.
High Internal Resistance can be achieved by programming the respective times to a
higher value, or the possible maximum. This is preferable when using analog sources
and supply with a high internal resistance in order to keep the current as low as possible.
The conversion rate in this case may be considerably lower, however.
Control Bitfields
For the timing control of the conversion and the sample phase two mechanisms are
provided:
• Standard timing control uses two 2-bit fields in register ADC_CON to select
prescaler values for the general conversion timing and the duration of the sample
phase. This provides compact control, while limiting the prescaler factors to a few
steps.
• Improved timing control uses two 6-bit fields in register ADC_CON1 (compatibility
mode) or register ADC_CTR2/ADC_CTR2IN (enhanced mode). This provides a wide
range of prescaler factors, so the ADC can be better adjusted to the internal and
external system circumstances.
Improved timing control is selected by setting bit ICST in register ADC_CON1 in
compatibility mode, or by selecting enhanced mode.
User’s Manual
ADC_X41, V2.1
16-18
V2.1, 2004-03