XC164-16 Datasheet, PDF (33/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
Timers T2 and T4 in Counter Mode
Counter mode for an auxiliary timer Tx is selected by setting bitfield TxM in register
TxCON to 001_B. In counter mode, an auxiliary timer can be clocked either by a transition
at its external input line TxIN, or by a transition of timer T3’s toggle latch T3OTL. The
event causing an increment or decrement of a timer can be a positive, a negative, or both
a positive and a negative transition at either the respective input pin or at the toggle latch.
Bitfield TxI in control register TxCON selects the triggering transition (see Table 14-5).
TxIN
T3
Toggle
Latch
0
MUX
1
Edge
Select
TxI.2
TxI
0
TxR
MUX
1
T3R
Count
Auxiliary
Timer Tx
TxIRQ
TxUD
TxEUD
TxRC
0
MUX _Up/Down
=1
1
TxUDE
x = 2, 4
MCB05397
Figure 14-13 Block Diagram of an Auxiliary Timer in Counter Mode
Table 14-5
T2I/T4I
X00
001
010
011
101
110
111
GPT1 Auxiliary Timer (Counter Mode) Input Edge Selection
Triggering Edge for Counter Increment/Decrement
None. Counter Tx is disabled
Positive transition (rising edge) on TxIN
Negative transition (falling edge) on TxIN
Any transition (rising or falling edge) on TxIN
Positive transition (rising edge) of T3 toggle latch T3OTL
Negative transition (falling edge) of T3 toggle latch T3OTL
Any transition (rising or falling edge) of T3 toggle latch T3OTL
Note: Only state transitions of T3OTL which are caused by the overflows/underflows of
T3 will trigger the counter function of T2/T4. Modifications of T3OTL via software
will NOT trigger the counter function of T2/T4.
User’s Manual
GPT_X41, V2.0
14-20
V2.1, 2004-03