XC164-16 Datasheet, PDF (326/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
TwinCAN Module
according to the FIFO rules is allowed as long as the limit of 32 message objects
is not exceeded.
21.1.5.1 Buffer Access by the CAN Controller
The data transfer between the message buffer and the CAN bus is managed by the
associated CAN controller. Each buffer is controlled by a FIFO algorithm (First In, First
Out = First Overwritten) storing messages, delivered by the CAN controller, in a circular
order.
CAN Pointer
= base + 0
CAN Pointer
= base + 7
CAN Pointer
= base + 1
CAN Pointer
= base + 2
(slave)
Element
1
(slave)
Element
2
Element
0
(base)
(slave)
Element
7
Element
3
(slave)
(slave)
Element
4
Element
6
(slave)
Element
5
(slave)
CAN Pointer
= base + 3
CAN Pointer
= base + 4
CAN Pointer
= base + 6
CAN Pointer
= base + 5
MCA05484
Figure 21-14 Structure of a FIFO Buffer with one Base Object and Seven Slave
Objects
If the FIFO buffer was initialized with receive objects, the first accepted message is
stored in the base message object (number n), the second message is written to buffer
element (n+1) and so on. The number of the element, used to store the next input
message, is indicated by bitfield CANPTR in control register MSGFGCRn of the base
object. If the reserved buffer space has been used up, the base message object
(followed by the consecutive slave objects) is addressed again to store the next incoming
message. When a message object was not read out on time by the CPU, the previous
User’s Manual
TwinCAN_X41, V2.1
21-26
V2.1, 2004-03