XC164-16 Datasheet, PDF (263/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Asynchronous/Synchronous Serial Interface (ASC)
Table 19-12 ASC Interrupt Sources (cont’d)
Interrupt
Signal Description
Receive
Interrupt
RIR
The interrupt is generated when the received frame is copied
from the receive shift register to the receive buffer register. If
a FIFO is configured for the ASC and bit RXTMEN is cleared,
RXFIFL defines when the interrupt is generated depending on
the FIFO fill state.
Note: Only for Asynchronous Modes
Receive Error RIR and The interrupt is generated when the received frame is copied
Interrupt
EIR
from the receive shift register to the receive buffer register and
the receive buffer contains already valid data.
Note: Only for Synchronous Mode
Receive
Overflow
RIR and If an additional frame is received when the FIFO is completely
EIR
full an overflow error occurs. Both interrupts are generated
and the previously received frame is overwritten in the FIFO
and therefore lost.
Read to
EIR
empty FIFO
A read operation from the CPU to an empty receive FIFO
generates this interrupt.
Transparent RIR
Read
Operation
In Transparent Mode a receive interrupt is always generated
on a read operation from the CPU to the receive FIFO if the
FIFO is not empty after this operation.
Flush Action TBIR
A transmit buffer interrupt is generated when the transmit
FIFO is flushed.
FIFO Enable TBIR
A transmit buffer interrupt is generated when the transmit
FIFO is enabled by setting bits TXTMEN and TXFEN when it
was previously disabled in Transparent Mode.
Transmit
Overflow
EIR
If an additional frame is written to the transmit FIFO when it is
completely full an overflow error occurred. The interrupt is
generated and the previously written frame is overwritten and
therefor lost in the FIFO.
Frame Error RIR and An expected stop bit is not high.
EIR
Note: Asynchronous Mode only
Parity Error RIR and When a parity bit is received that does not fit to the parity of
EIR
the received data.
Note: Asynchronous Mode only
User’s Manual
ASC_X, V2.0
19-38
V2.1, 2004-03