XC164-16 Datasheet, PDF (310/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
TwinCAN Module
Calculation of the Bit Time
t_q = (BRP + 1) / f_CAN, if DIV8X = ‘0’
= (BRP + 1) / 8 × f_CAN, if DIV8X = ‘1’
T_Sync = 1 t_q
T_Seg1 = (TSEG1 + 1) × t_q (min. 3 t_q)
T_Seg2 = (TSEG2 + 1) × t_q (min. 2 t_q)
bit time = T_Sync + T_Seg1 + T_Seg2 (min. 8 t_q)
To compensate phase shifts between clocks of different CAN controllers, the CAN
controller has to synchronize on any edge from the recessive to the dominant bus level.
If the hard synchronization is enabled (at the start of frame), the bit time is restarted at
the synchronization segment. Otherwise, the resynchronization jump width T_SJW defines
the maximum number of time quanta a bit time may be shortened or lengthened by one
resynchronization. The value of SJW is programmed in the ABTR/BBTR registers.
T_SJW = (SJW + 1) × t_q
T_Seg1 ≥ T_SJW + T_prop
T_Seg2 ≥ T_SJW
The maximum relative tolerance for f_CAN depends on the phase buffer segments and the
resynchronization jump width.
df_CAN ≤ min (T_b1, T_b2) / 2 × (13 × bit time - T_b2) AND
df_CAN ≤ T_SJW / 20 × bit time
Calculation of the Baudrate
Baudrate = f_CAN / ((BRP + 1) × (1 + T_Seg1 + T_Seg2))
User’s Manual
TwinCAN_X41, V2.1
21-10
V2.1, 2004-03