XC164-16 Datasheet, PDF (262/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Asynchronous/Synchronous Serial Interface (ASC)
The two autobaud interrupt request lines (start of autobaud detection and end of
autobaud detection) in each ASC module are ‘ORed’ together; the ‘ORed’ output signal
is connected to the interrupt control register. This is shown in Figure 19-20.
ASCx
Kernel
start_autobaud_detect_irq
>^_ 1
end_autobaud_detect_irq
ASCx_ABIC
(x = 0 … 1)
MCA05451
Figure 19-20 Wiring of Autobaud Interrupts
Table 19-12 summarizes all interrupt sources:
Table 19-12 ASC Interrupt Sources
Interrupt
Signal Description
TBUF Action TBIR
A write action to the transmit shift register from the transmit
buffer register ASCx_TBUF.
If a FIFO is configured for the ASC and bit TXTMEN is
cleared, TXFIFL defines when the interrupt is generated
depending on the FIFO fill state.
Transmit
Interrupt
TIR
The interrupt is generated after the last (eight) data bit of a
transmission frame is send via line TxD by the transmit shift
register.
Note: Only for Synchronous Mode
Transmit
Interrupt
TIR
The interrupt is generated just before the last bit of a
transmission frame is send via line TxD by the transmit shift
register. If a FIFO is configured for the ASC and bit XTMEN is
cleared, TXFIFL defines when the interrupt is generated
depending on the FIFO fill state.
Note: Only for Asynchronous Modes
Receive
Interrupt
RIR
The interrupt is generated when the received frame is copied
from the receive shift register to the receive buffer register.
Note: Only for Synchronous Mode
User’s Manual
ASC_X, V2.0
19-37
V2.1, 2004-03