XC164-16 Datasheet, PDF (327/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
TwinCAN Module
message data is overwritten, which is indicated by flag MSGLST in the corresponding
MSGCTR register.
If the FIFO buffer was initialized with transmit message objects, the CAN controller starts
the transfer with the contents of buffer element 0 (FIFO base object) and increments
bitfield CANPTR in control register MSGFGCRn, pointing to the next element to be
transmitted.
If the message object, which is currently addressed by the base object’s CANPTR, is not
valid (MSGVAL = ‘01’), the FIFO is not enabled for data transfer. In this case, the
MSGVAL bitfields of the other FIFO elements (including the base element if not currently
addressed) are not taken into account.
In the case that the MSGVAL bitfields are set to ‘10’ for the FIFO base object and ‘01’ for
the currently addressed FIFO slave object, the data will not be delivered to the slave
object, whereas the bitfield CANPTR in the FIFO base object is incremented according
to FIFO rules.
If the FIFO is set up for the transmission of data frames and a matching remote frame is
detected for one of the elements of the FIFO, the transmit request and remote pending
bits will be set automatically in the corresponding message object. The transmission of
the requested data frame is handled according to the FIFO rules and the value of the
CANPTR bitfield in the FIFO base object.
21.1.5.2 Buffer Access by the CPU
The message transfer between a buffer and the CPU has to be managed by software.
All message objects, combined to a buffer, can be accessed directly by the CPU. Bitfield
CANPTR in control register MSGFGCRn is not automatically modified by a CPU access
to the message object registers.
User’s Manual
TwinCAN_X41, V2.1
21-27
V2.1, 2004-03