XC164-16 Datasheet, PDF (57/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
T5IN
T6
Toggle
Latch
0
MUX
1
Edge
Select
T5I.2
T5I
0
T5R
MUX
1
T6R
Count
Auxiliary
Timer T5
Clear
T5IRQ
T5UD
T5EUD
T5RC
0
MUX
=1
1
Up/Down
T5UDE
MCB05408_X4
Figure 14-27 Block Diagram of Auxiliary Timer T5 in Counter Mode
Table 14-13 GPT2 Auxiliary Timer (Counter Mode) Input Edge Selection
T5I
Triggering Edge for Counter Increment/Decrement
X00
None. Counter T5 is disabled
001
Positive transition (rising edge) on T5IN
010
Negative transition (falling edge) on T5IN
011
Any transition (rising or falling edge) on T5IN
101
Positive transition (rising edge) of T6 toggle latch T6OTL
110
Negative transition (falling edge) of T6 toggle latch T6OTL
111
Any transition (rising or falling edge) of T6 toggle latch T6OTL
Note: Only state transitions of T6OTL which are caused by the overflows/underflows of
T6 will trigger the counter function of T5. Modifications of T6OTL via software will
NOT trigger the counter function of T5.
For counter operation, pin T5IN must be configured as input (the respective direction
control bit DPx.y must be 0). The maximum input frequency allowed in counter mode
depends on the selected prescaler value. To ensure that a transition of the count input
signal applied to T5IN is recognized correctly, its level must be held high or low for a
minimum number of module clock cycles before it changes. This information can be
found in Section 14.2.6.
User’s Manual
GPT_X41, V2.0
14-44
V2.1, 2004-03