XC164-16 Datasheet, PDF(128/417 Page) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

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XC164-16 Datasheet, PDF (128/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

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XC164-16 Derivatives

Peripheral Units (Vol. 2 of 2)

Capture/Compare Units

compare modes for the two registers of a pair. The bank1 register must be programmed

for mode 1 (with port influence), while the bank2 register must be programmed for

mode 0 (interrupt-only).

Double-register compare mode can be controlled (this means, enabled or disabled) for

each register pair via the associated control bitfield DRxM in register CC1_DRM or

CC2_DRM, respectively.

CC1_DRM

Double-Reg. Cmp. Mode Reg.

15 14 13 12 11 10

SFR (FF5AH/ADH)

9876

DR7M

rw

DR6M

rw

DR5M

rw

DR4M

rw

DR3M

rw

54

DR2M

rw

Reset Value: 0000H

3210

DR1M

rw

DR0M

rw

CC2_DRM

Double-Reg. Cmp. Mode Reg.

15 14 13 12 11 10

SFR (FF2AH/95H)

9876

DR7M

rw

DR6M

rw

DR5M

rw

DR4M

rw

DR3M

rw

Reset Value: 0000H

543210

DR2M

rw

DR1M

rw

DR0M

rw

Field

DRxM

Bits

[1:0],

[3:2],

[5:4],

[7:6],

[9:8],

[11:10],

[13:12],

[15:14]

Type

rw

Description

Double Register x Compare Mode Selection

00 DRM is controlled via the combination of compare

modes 1 and 0 (compatibility mode)

01 DRM disabled regardless of compare modes

10 DRM enabled regardless of compare modes

11 Reserved

Note: âxâ indicates the register pair index in a bank.

Double-register compare mode can be controlled individually for each of the register

pairs.

In the block diagram of the double-register compare mode (Figure 17-10), a bank2

register will be referred to as CCz, while the corresponding bank1 register will be referred

to as CCy.

Userâs Manual

CC12_X41, V2.1

17-23

V2.1, 2004-03

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