XC164-16 Datasheet, PDF (174/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Capture/Compare Unit 6 (CAPCOM6)
T13STR T13TEC T13RR
T13STD T13TED T13RS
f
CC6
n
T13CLK
256
MUX f_{T13 Counter Register}
T13
T13
Control
& Status
T13PRE
= 0000_H
Comp.
=?
Read-Only
Period Register
T13PR
T13R
STE13
T13RES
T13SSC
T13_ZM
T13_PM
T13_ST
Write-Only
Period Shadow
Register T13PS
MCA05527
Figure 18-23 T13 Counter Logic and Period Comparators
The start or stop of T13 is controlled by the Run bit, T13R. This control bit can be set by
software via the associated set/reset bits T13RS or T13RR, or it is reset by hardware
according to preselected conditions.
Timer T13 can be cleared to 0000_H via control bit T13RES. Setting this write-only bit only
clears the timer contents, but has no further effects, e.g., it does not stop the timer.
The generation of the T13 shadow transfer control signal, T13_ST, is enabled via bit
STE13. This bit can be set or reset by software indirectly through its associated set/reset
control bits T13STR and T13STD.
Two bitfields, T13TEC and T13TED, control the synchronization of T13 to Timer T12
events. T13TEC selects the trigger event, while T13TED determines for which T12 count
direction the trigger should be active.
Note: The T13 Period Register and its associated shadow register are located at the
same physical address. A write access to this address targets the Shadow
Register, while a read access reads from the actual period register.
User’s Manual
CAPCOM6_X, V2.0
18-30
V2.1, 2004-03