XC164-16 Datasheet, PDF (43/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
14.1.7 Interrupt Control for GPT1 Timers
When a timer overflows from FFFF_H to 0000_H (when counting up), or when it underflows
from 0000_H to FFFF_H (when counting down), its interrupt request flag (T2IR, T3IR or
T4IR) in register TxIC will be set. This will cause an interrupt to the respective timer
interrupt vector (T2INT, T3INT or T4INT) or trigger a PEC service, if the respective
interrupt enable bit (T2IE, T3IE or T4IE in register TxIC) is set. There is an interrupt
control register for each of the three timers.
GPT12E_T2IC
Timer 2 Intr. Ctrl. Reg.
SFR (FF60_H/B0_H)
15 14 13 12 11 10 9 8 7 6 5
- - - - - - - GPX T2IR T2IE
- - - - - - - rw rwh rw
Reset Value: - - 00_H
43210
ILVL
rw
GLVL
rw
GPT12E_T3IC
Timer 3 Intr. Ctrl. Reg.
SFR (FF62_H/B1_H)
15 14 13 12 11 10 9 8 7 6 5
- - - - - - - GPX T3IR T3IE
- - - - - - - rw rwh rw
Reset Value: - - 00_H
43210
ILVL
rw
GLVL
rw
GPT12E_T4IC
Timer 4 Intr. Ctrl. Reg.
SFR (FF64_H/B2_H)
Reset Value: - - 00_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- - - - - - - GPX T4IR T4IE
ILVL
GLVL
- - - - - - - rw rwh rw
rw
rw
Note: Please refer to the general Interrupt Control Register description for an
explanation of the control fields.
User’s Manual
GPT_X41, V2.0
14-30
V2.1, 2004-03