XC164-16 Datasheet, PDF (149/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Capture/Compare Unit 6 (CAPCOM6)
Two further signals indicate whether the counter contents are equal to 0000_H (T12_ZM)
or 0001_H (T12_OM). These signals control the counting and switching behavior of T12.
The basic operating mode of T12, either Edge-Aligned mode (Figure 18-5) or Center-
Aligned mode (Figure 18-6), is selected via bit CTM. A Single-Shot control bit, T12SSC,
enables an automatic stop of the timer when the current counting period is finished (see
Figure 18-7 and Figure 18-8).
T12STR
T12RR
T12STD CTM T12RS
f_CC6
n
T12CLK
256
MUX f_{T12 Counter Register}
T12
T12PRE
Comp.
=?
= 0000_H
= 0001_H
T12
Control
& Status
Read-Only
Period Register
T12PR
T12R
CDIR
STE12
T12RES
T12SSC
T12_ZM
T12_OM
T12_PM
T12_SSEP
T12_ST
Write-Only
Period Shadow
Register T12PR
MCA05508
Figure 18-4 Timer T12 Logic and Period Comparators
The start or stop of T12 is controlled by the Run bit, T12R. This control bit can be set by
software via the associated set/reset bits T12RS or T12RR, or it is reset by hardware
according to preselected conditions.
Timer T12 can be cleared via control bit T12RES. Setting this write-only bit does only
clear the timer contents, but has no further effects, for example, it does not stop the timer.
The generation of the T12 shadow transfer control signal, T12_ST, is enabled via bit
STE12. This bit can be set or reset by software indirectly through its associated set/reset
control bits T12STR and T12STD.
Note: The control registers to select the T12 operating mode are described in
Section 18.3.
User’s Manual
CAPCOM6_X, V2.0
18-5
V2.1, 2004-03