XC164-16 Datasheet, PDF (261/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Asynchronous/Synchronous Serial Interface (ASC)
Asynchronous Mode
TBIR
TIR
TBIR
Idle
Synchronous Mode
TBIR
RIR
TIR
TBIR
Idle
Asynchronous Modes
Autobaud Detection
ABSTIR
RIR
ABDETIR ¹⁾
Idle
1. Character
TIR
TBIR
RIR
TIR
TBIR
RIR
TIR
Idle
RIR
TIR
Idle
RIR
ABDETIR
2. Character
1) Only if FCDETEN = 1
MCT05450
Figure 19-19 ASC Interrupt Generation
As shown in Figure 19-19, TBIR is an early trigger for the reload routine, while TIR
indicates the completed transmission. Therefore, software using handshake should rely
on TIR at the end of a data block to ensure that all data has actually been transmitted.
The six interrupts of the ASC0 and of the ASC1 module are controlled by the following
service request control registers:
• ASC0_ABIC, ASC1_ABIC: control the autobaud interrupts
• ASC0_TIC, ASC1_TIC: control the transmit interrupts
• ASC0_RIC, ASC1_RIC: control the receive interrupts
• ASC0_EIC, ASC1_EIC: control the error interrupts
• ASC0_TBIC, ASC1_TBIC: control the transmit buffer empty interrupt
Note: Please refer to the general Interrupt Control Register description for an
explanation of the control fields.
User’s Manual
ASC_X, V2.0
19-36
V2.1, 2004-03