XC164-16 Datasheet, PDF (276/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Asynchronous/Synchronous Serial Interface (ASC)
Receive FIFO Control Register
ASCx_RXFCON
Receive FIFO Control Reg.
ESFR (Table 19-13)
15 14 13 12 11 10 9 8 7 6 5
-
RXFITL
-
-
rw
-
Reset Value: 0100_H
43210
RX
TM
EN
RXF RXF
FLU EN
rw rw rw
Field
RXFITL
RXTMEN
Bits
[11:8]
2
Type
rw
rw
Description
Receive FIFO Interrupt Trigger Level
Defines a receive FIFO interrupt trigger level. A
receive interrupt request (RIR) is generated after the
reception of a byte when the filling level of the receive
FIFO is equal to or greater than RXFITL.
0000 Reserved. Do not use this combination
0001 Interrupt trigger level is set to one
0010 Interrupt trigger level is set to two
……
0111 Interrupt trigger level is set to seven
1000 Interrupt trigger level is set to eight
Note: In Transparent Mode this bitfield is don’t care.
Note: Combinations defining an interrupt trigger level
greater than the FIFO size should not be used.
Receive FIFO Transparent Mode Enable
0 Receive FIFO Transparent Mode is disabled
1 Receive FIFO Transparent Mode is enabled
Note: This bit is don’t care if the receive FIFO is
disabled (RXFEN = 0).
User’s Manual
ASC_X, V2.0
19-51
V2.1, 2004-03