XC164-16 Datasheet, PDF (129/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Capture/Compare Units
Timer T0/T7
Timer T1/T8
ACCy
ACCz
DRyM
MODy
Mode
Control
SEEy SEMy
DRyM
MODz
Mode
Control
Comp.
=?
Comparator
=?
Mode &
Output Ctrl.
CCyIRQ
to Port
Logic
CCzIRQ
SEEz SEMz
Compare
Register CCy
Compare
Register CCz
z=y+8
MCB05426
Figure 17-10 Double-Register Compare Mode Block Diagram
When a match is detected for one of the two registers in a register pair (CCy or CCz),
the associated interrupt request line (CCyIRQ or CCzIRQ) is activated, and pin CCyIO,
corresponding to the bank1 register CCy, is toggled. The generated interrupt always
corresponds to the register that caused the match.
Note: If a match occurs simultaneously for both register CCy and register CCz of the
register pair, pin CCyIO will be toggled only once, but two separate compare
interrupt requests will be generated.
Each of the two registers of a pair can be individually allocated to one of the two timers
in the CAPCOM unit. This offers a wide variety of applications, as the two timers can run
in different modes with different resolution and frequency. However, this might require
sophisticated software algorithms to handle the different timer periods.
Note: The signals CCzIO (which do not serve for double-register compare mode) may
be used for general purpose IO.
User’s Manual
CC12_X41, V2.1
17-24
V2.1, 2004-03