XC164-16 Datasheet, PDF (23/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
Counter Mode
Counter Mode for the core timer T3 is selected by setting bitfield T3M in register T3CON
to 001_B. In counter mode, timer T3 is clocked by a transition at the external input pin
T3IN. The event causing an increment or decrement of the timer can be a positive, a
negative, or both a positive and a negative transition at this line. Bitfield T3I in control
register T3CON selects the triggering transition (see Table 14-2).
T3IN
T3UD
T3EUD
Edge
Select
T3I
=1
Count
Core Timer T3
T3R
0
MUX _Up/Down
1
Toggle Latch
T3UDE
Figure 14-6 Block Diagram of Core Timer T3 in Counter Mode
T3IRQ
T3OUT
to
T2/T4
MCB05393
Table 14-2 GPT1 Core Timer T3 (Counter Mode) Input Edge Selection
T3I
Triggering Edge for Counter Increment/Decrement
000
None. Counter T3 is disabled
001
Positive transition (rising edge) on T3IN
010
Negative transition (falling edge) on T3IN
011
Any transition (rising or falling edge) on T3IN
1XX
Reserved. Do not use this combination
For counter mode operation, pin T3IN must be configured as input (the respective
direction control bit DPx.y must be 0). The maximum input frequency allowed in counter
mode depends on the selected prescaler value. To ensure that a transition of the count
input signal applied to T3IN is recognized correctly, its level must be held high or low for
a minimum number of module clock cycles before it changes. This information can be
found in Section 14.1.5.
User’s Manual
GPT_X41, V2.0
14-10
V2.1, 2004-03