XC164-16 Datasheet, PDF(232/417 Page) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

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XC164-16 Datasheet, PDF (232/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

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XC164-16 Derivatives

Peripheral Units (Vol. 2 of 2)

Asynchronous/Synchronous Serial Interface (ASC)

9-Bit Data Frames

9-bit data frames consist of either nine data bits D8 â¦ D0 (M = 100B), eight data bits

D7 â¦ D0 plus an automatically generated parity bit (M = 111B), or eight data bits

D7 â¦ D0 plus wake-up bit (M = 101B). Parity may be odd or even, depending on bit

ODD. An even parity bit will be set if the modulo-2-sum of the 8 data bits is 1. An odd

parity bit will be cleared in this case. Parity checking is enabled via bit PEN (always OFF

in 9-bit data and wake-up mode). The parity error flag PE will be set, along with the error

interrupt request flag, if a wrong parity bit is received. The parity bit itself will be stored

in bit RBUF.8.

Start

Bit

0

D0

LSB

D1

11-/12-bit UART Frame

9 Data Bits

D2 D3 D4 D5 D6

11

(1st) (2nd)

D7 Bit 9 Stop Stop

Bit Bit

CON.M = 100B : Bit 9 = Data Bit D8

CON.M = 101B : Bit 9 = Wake-up Bit

CON.M = 111B : Bit 9 = Parity Bit

MCT05436

Figure 19-5 Asynchronous 9-Bit Frames

In wake-up mode, received frames are transferred to the receive buffer register only if

the 9th bit (the wake-up bit) is 1. If this bit is 0, no receive interrupt request will be

activated and no data will be transferred.

This feature may be used to control communication in a multi-processor system:

When the master processor wants to transmit a block of data to one of several slaves, it

first sends out an address byte to identify the target slave. An address byte differs from

a data byte in that the additional 9th bit is a 1 for an address byte, but is a 0 for a data

byte; so, no slave will be interrupted by a data âbyteâ. An address âbyteâ will interrupt all

slaves (operating in 8-bit data + wake-up bit mode), so each slave can examine the eight

LSBs of the received character (the address). The addressed slave will switch to 9-bit

data mode (such as by clearing bit M[0]), to enable it to also receive the data bytes that

will be coming (having the wake-up bit cleared). The slaves not being addressed remain

in 8-bit data + wake-up bit mode, ignoring the following data bytes.

Userâs Manual

ASC_X, V2.0

19-7

V2.1, 2004-03

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