XC164-16 Datasheet, PDF (306/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
TwinCAN Module
21.1.2.3 Global Control and Status Logic
The receive interrupt pending register RXIPND contains 32 individual flags indicating a
pending receive interrupt for the associated message objects. Flag RXIPNDn is set by
hardware if the corresponding message object has correctly received a data or remote
frame and the correlated interrupt request generation has been enabled by RXIEn = ‘10’.
RXIPNDn can be cleared by software by resetting bit INTPNDn in the corresponding
message object control register MSGCTRn.
The transmit interrupt pending register TXIPND has a similar functionality as the
RXIPND register and provides identical information about pending transmit interrupts.
User’s Manual
TwinCAN_X41, V2.1
21-6
V2.1, 2004-03