XC164-16 Datasheet, PDF (311/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
TwinCAN Module
21.1.3.3 Bitstream Processor
Based on the objects in the message buffer, the bitstream processor generates the
remote and data frames to be transmitted via the CAN bus. It controls the CRC generator
and adds the checksum information to the new remote or data frame. After including the
start of frame bit SOF and the end of frame field EOF, the bitstream processor starts the
CAN bus arbitration procedure and continues with the frame transmission when the bus
was found in idle state. While the data transmission is running, the bitstream processor
monitors continuously the I/O line. If (outside the CAN bus arbitration phase or the
acknowledge slot) a mismatch is detected between the voltage level on the I/O line and
the logic state of the bit currently sent out by the transmit shift register, a last error
interrupt request is generated and the error code is indicated by bitfield LEC in status
register ASR/BSR.
An incoming frame is verified by checking the associated CRC field. When an error has
been detected, the last error interrupt request is generated and the associated error code
is presented in status register ASR/BSR. Furthermore, an error frame is generated and
transmitted on the CAN bus. After decomposing a faultless frame into identifier and data
portion, the received information is transferred to the message buffer executing remote
and data frame handling, interrupt generation and status processing.
21.1.3.4 Error Handling Logic
The error handling logic is responsible for the fault confinement of the CAN device. Its
two counters, the receive error counter and the transmit error counter (control registers
AECNT, BECNT), are incremented and decremented by commands from the bit stream
processor. If the bit stream processor itself detects an error while a transmit operation is
running, the transmit error counter is incremented by 8. An increment of 1 is used, when
the error condition was reported by an external CAN node via an error frame generation.
For error analysis, the transfer direction of the disturbed message and the node,
recognizing the transfer error, are indicated in the control registers AECNT, BECNT.
According to the values of the error counters, the CAN controller is set into the states
error-active, error-passive or bus-off.
The CAN controller is in error-active state, if both error counters are below the error-
passive limit of 128. It is in error-passive state, if at least one of the error counters equals
or exceeds 128.
The bus-off state is activated if the transmit error counter equals or exceeds the bus-off
limit of 256. This state is reported by flag BOFF in the ASR/BSR status register. The
device remains in this state, until the bus-off recovery sequence is finished. Additionally,
there is the bit EWRN in the ASR/BSR status register, which is set if at least one of the
error counters equals or exceeds the error warning limit defined by bitfield EWRNLVL in
the control registers AECNT, BECNT. Bit EWRN is reset if both error counters fall below
the error warning limit again.
User’s Manual
TwinCAN_X41, V2.1
21-11
V2.1, 2004-03