XC164-16 Datasheet, PDF (17/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
14.1.1 GPT1 Core Timer T3 Control
The current contents of the core timer T3 are reflected by its count register T3. This
register can also be written to by the CPU, for example, to set the initial start value.
The core timer T3 is configured and controlled via its bitaddressable control register
T3CON.
GPT12E_T3CON
Timer 3 Control Register
SFR (FF42_H/A1_H)
Reset Value: 0000_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T3 T3 T3
R CH ED
DIR DIR GE
BPS1
T3
OTL
T3
OE
T3
UDE
T3
UD
T3R
T3M
T3I
rh rwh rwh
rw
rwh rw rw rw rw
rw
rw
Field
T3RDIR
T3CHDIR
T3EDGE
BPS1
T3OTL
Bits Type
15
rh
14
rwh
13
rwh
[12:11] rw
10
rwh
Description
Timer T3 Rotation Direction Flag
0 Timer T3 counts up
1 Timer T3 counts down
Timer T3 Count Direction Change Flag
This bit is set each time the count direction of timer
T3 changes. T3CHDIR must be cleared by SW.
0 No change of count direction was detected
1 A change of count direction was detected
Timer T3 Edge Detection Flag
The bit is set each time a count edge is detected.
T3EDGE must be cleared by SW.
0 No count edge was detected
1 A count edge was detected
GPT1 Block Prescaler Control
Selects the basic clock for block GPT1
(see also Section 14.1.5)
00 f_GPT/8
01 f_GPT/4
10 f_GPT/32
11 f_GPT/16
Timer T3 Overflow Toggle Latch
Toggles on each overflow/underflow of T3. Can be
set or reset by software (see separate description)
User’s Manual
GPT_X41, V2.0
14-4
V2.1, 2004-03