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| XC164-16 Datasheet, PDF (256/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units | |||
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XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Asynchronous/Synchronous Serial Interface (ASC)
According to Table 19-8 a baudrate of 9600 bit/s is achieved when register ASCx_BG is
loaded with a value of 047H, assuming that fDIV has been set to 11.0592 MHz.
Table 19-8 also lists a divide factor df which is defined with the following formula:
Baudrate = f---D---I-V-
df
(19.2)
This divide factor df defines a fixed relationship between the prescaler output frequency
fDIV and the baudrate to be detected during the Autobaud Detection operation. This
means, changing fDIV results in a totally different baudrate table in means of baudrate
values. For the baudrates to be detected, the following relations are always valid:
Br0 = fDIV/48D, Br1 = fDIV/96D, ⦠up to Br8 = fDIV/9216D
A requirement for detecting standard baudrates up to 230.400 kbit/s is the fDIV minimum
value of 11.0592 MHz. With the value FD_VALUE the fractional divider fDIV is adapted to
the module clock frequency fASC. Table 19-9 defines the deviation of the standard
baudrates when using autobaud detection depending on the module clock fASC.
Table 19-9 Standard Baudrates - Deviations and Errors for Autobaud Detection
fASC
10 MHz
FDV
Error in fDIV
not possible
12 MHz
472
+0.03%
13 MHz
436
+0.1%
16 MHz
354
+0.03%
18 MHz
315
+0.14%
18.432 MHz
307
-0.07%
20 MHz
283
-0.04%
24 MHz
236
+0.03%
25 MHz
226
-0.22%
30 MHz
189
+0.14%
33 MHz
172
+0.24%
40 MHz
142
+0.31%
Note: If the deviation of the baudrate after autobaud detection is to high, the baudrate
generator (fractional divider FDV and reload register ASCx_BG) can be
reprogrammed if required to get a more precise baudrate with less error.
Userâs Manual
ASC_X, V2.0
19-31
V2.1, 2004-03
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