XC164-16 Datasheet, PDF (25/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
Table 14-3
T3I
000
001
010
011
1XX
Core Timer T3 (Incremental Interface Mode) Input Edge Selection
Triggering Edge for Counter Increment/Decrement
None. Counter T3 stops.
Any transition (rising or falling edge) on T3IN.
Any transition (rising or falling edge) on T3EUD.
Any transition (rising or falling edge) on any T3 input (T3IN or T3EUD).
Reserved. Do not use this combination.
The incremental encoder can be connected directly to the XC164 without external
interface logic. In a standard system, however, comparators will be employed to convert
the encoder’s differential outputs (such as A, A) to digital signals (such as A). This greatly
increases noise immunity.
Note: The third encoder output T0, which indicates the mechanical zero position, may
be connected to an external interrupt input and trigger a reset of timer T3 (for
example via PEC transfer from ZEROS).
Encoder
A
A
B
B
T0
T0
Signal
Conditioning
A
B
T0
Controller
T3Input
T3Input
Interrupt
MCS04372
Figure 14-8 Connection of the Encoder to the XC164
For incremental interface operation, the following conditions must be met:
• Bitfield T3M must be 110_B or 111_B.
• Both pins T3IN and T3EUD must be configured as input, i.e. the respective direction
control bits must be 0.
• Bit T3UDE must be 1 to enable automatic external direction control.
The maximum count frequency allowed in incremental interface mode depends on the
selected prescaler value. To ensure that a transition of any input signal is recognized
correctly, its level must be held high or low for a minimum number of module clock cycles
before it changes. This information can be found in Section 14.1.5.
User’s Manual
GPT_X41, V2.0
14-12
V2.1, 2004-03