XC164-16 Datasheet, PDF (39/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
Auxiliary Timer in Capture Mode
Capture mode for an auxiliary timer Tx is selected by setting bitfield TxM in the respective
register TxCON to 101_B. In capture mode, the contents of the core timer T3 are latched
into an auxiliary timer register in response to a signal transition at the respective auxiliary
timer’s external input pin TxIN. The capture trigger signal can be a positive, a negative,
or both a positive and a negative transition.
The two least significant bits of bitfield TxI select the active transition (see Table 14-5).
Bit 2 of TxI is irrelevant for capture mode and must be cleared (TxI.2 = 0).
Note: When programmed for capture mode, the respective auxiliary timer (T2 or T4)
stops independently of its run flag T2R or T4R.
f
GPT
T3IN
Operating
Mode
Control
BPS1 T3I
Count
Core Timer T3
Toggle Latch
T3IRQ
T3OUT
T3R
Up/Down
to Ty
TxIN
Edge
Capture
Select
TxIRQ
TxI
Auxiliary
Timer Tx
x = 2, 4
y = 4, 2
MCA05402
Figure 14-18 GPT1 Auxiliary Timer in Capture Mode
Upon a trigger (selected transition) at the corresponding input pin TxIN the contents of
the core timer are loaded into the auxiliary timer register and the associated interrupt
request flag TxIR will be set.
For capture mode operation, the respective timer input pin TxIN must be configured as
input. To ensure that a transition of the capture input signal applied to TxIN is recognized
correctly, its level must be held high or low for a minimum number of module clock
cycles, detailed in Section 14.1.5.
User’s Manual
GPT_X41, V2.0
14-26
V2.1, 2004-03